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Espressif Systems /ESP32-S3 /RMT /CH7_RX_CONF1

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Interpret as CH7_RX_CONF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_EN)RX_EN 0 (MEM_WR_RST)MEM_WR_RST 0 (APB_MEM_RST)APB_MEM_RST 0 (MEM_OWNER)MEM_OWNER 0 (RX_FILTER_EN)RX_FILTER_EN 0RX_FILTER_THRES0 (MEM_RX_WRAP_EN)MEM_RX_WRAP_EN 0 (AFIFO_RST)AFIFO_RST 0 (CONF_UPDATE)CONF_UPDATE

Description

Channel 7 configure register 1

Fields

RX_EN

Set this bit to enable receiver to receive data on CHANNEL%s.
MEM_WR_RST

Set this bit to reset write ram address for CHANNEL%s by accessing receiver.
APB_MEM_RST

Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.
MEM_OWNER

This register marks the ownership of CHANNEL%s’s ram block.

1’h1: Receiver is using the ram.

1’h0: APB bus is using the ram.
RX_FILTER_EN

This is the receive filter’s enable bit for CHANNEL%s.
RX_FILTER_THRES

Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).
MEM_RX_WRAP_EN

This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size.
AFIFO_RST

Reserved
CONF_UPDATE

synchronization bit for CHANNEL%s

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data